The present invention relates to an image memory system provided with image memories for odd field data and even field data, respectively, and particularly to control of the image memories when the total number of dots on one line of image data is not divisible without remainder by the number of dots simultaneously written in the image memories in parallel.
In the conventional image memory system, for example, as described in the Japanese Laid-Open Patent Application (KOKAI) 1-142987, "Image Display Apparatus", an image memory is divided into a plurality of banks so that image data from a host processor are successively written into the respective banks. In reading out the image data from the banks, the image data in the respective banks are data-converted in the look-up table, and the parallel image data outputted from the respective look-up tables is converted by interleaving in a parallel-to-serial converter into serial image data so as to display the image. With this structure, it is possible to provide a high-accuracy display device, which utilizes a high-speed pixel rate which cannot normally be employed owing to the limit of the access speed of the SAM unit within the VRAM (video RAM), by using the VRAM which enhances efficiency of the drawing and displaying of the image data. Also, it is not necessary to provide high-speed look-up tables in the apparatus for the data conversion.
In this conventional technique, processing speed is substantially improved by the use of a plurality of banks as the image memory. However, there remains the problem that it is impossible to process a plurality of pixels from the memory of a computer at the same time, and also, there is no concern given to the method of controlling the remaining data when the total number of dots on one line of the image data is not divisible by the number of dots to be written into the image memories in parallel. Further, there is no disclosure as to the conversion in the scan system between non-interlace and interlace.